Electrically programmable and erasable memory array devices using floating gate for the storage or charges thereon are well known in the art. See, for example, U.S. Pat. No. 4,698,787.
In U.S. Pat. No. 5,029,130, assigned to the present assignee, which is incorporated herein by reference, a novel type of EEPROM or flash EEPROM memory device is disclosed. In that application, the programming and erase operation can be selectively performed on a single row. However, although the programming operation is selectively performed on a single row, there may be undesired disturbance on the same column lines. In U.S. Patent Application 682,459, filed on Apr. 9, 1991, which is also assigned to the present assignee and is incorporated herein by reference, another type of EEPROM memory device is disclosed. In that application, the memory array can be programmed and erased on a selective row basis. However, similar to the invention disclosed in U.S. Pat. No. 5,029,130, because programming is accomplished by high voltage, i.e., greater than 10 volts, the high voltage may disturb the unselected cells due to the common ground line.